1. Field of the Invention
The present invention relates to a shift register formed by cascading a plurality of master-slave flip-flops.
2. Description of Related Art
A shift register can be formed by cascading a plurality of flip-flops. For example, a master-slave flip-flop formed by cascading master and slave latches can be adopted as each of the flip-flops. The master latch and slave latch have configurations identical to each other and take in pieces of data in accordance with a master clock and a slave clock, respectively, to hold the pieces of data. Each flip-flop outputs data to a flip-flop in a next stage in synchronism with these clocks and holds transmitted data.
Examples of such a shift register include one proposed in Japanese Patent Application Laid-Open Publication No. 03-192600. Note that a data latch portion in a flip-flop configured to hold transmitted data can be formed by combining a plurality of gate circuits.
Along with microfabrication of transistors constituting a semiconductor device, tolerance for a soft error, which refers to a phenomenon in which data is erased by cosmic rays, radial rays, and the like, has recently been an issue. In order to ensure sufficient tolerance for a soft error, a transistor with a sufficiently large transistor size (a channel length (hereinafter referred to as L)) and a channel width (hereinafter referred to as W)) needs to be used as a transistor constituting a data latch portion of each flip-flop.
For this reason, a transistor cannot be formed to have minimum dimensions, and a circuit area of a conventional shift register becomes large.